Quantum well (QW) semiconductor devices based on group III-V materials, such as indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), can be formed on silicon (Si) substrates. These devices may use GaAs as a coating on a Si substrate to create a “virtual” polar substrate, which may result in a defect density greater than E8-E10/cm2. In addition, quantum well devices may use large bandgap indium aluminum arsenide (InAlAs) barrier layers for hole confinement in the InGaAs QW grown either on GaAs or indium phosphide (InP) substrates for p-channel quantum well field effect transistors (QWFETs) for the complementary part of the n-channel InGaAs QWFET . Such devices may suffer from low two-dimensional hole mobility due to the lower valence band offset between the QW and the barrier layer. This offset may result in poor hole confinement inside the InGaAs channel material. Further still, the devices may have defects (e.g., stacking faults and twins) and dislocations (e.g., threading dislocations) that propagate inside the quantum well due to, for example, lattice-mismatch issues as well as polar-on-nonpolar material growth on Si without the proper buffer layer architecture in between the QW and the starting substrate.